发明名称 Copper etching integration scheme
摘要 The present disclosure is directed to an integrated circuit. The integrated circuit has a conductive body disposed over a substrate. The conductive body has tapered sidewalls that cause an upper surface of the conductive body to have a greater width than a lower surface of the conductive body. The integrated circuit also has a projection disposed over the conductive body. The projection has tapered sidewalls that cause a lower surface of the projection to have a greater width than an upper surface of the projection and a smaller width than an upper surface of the conductive body. A dielectric material surrounds the conductive body and the projection.
申请公布号 US9633949(B2) 申请公布日期 2017.04.25
申请号 US201615153967 申请日期 2016.05.13
申请人 Taiwan Semiconductor Manufacturing Co., Ltd. 发明人 Lu Chih-Wei;Lee Chung-Ju;Lee Hsiang-Huan;Bao Tien-I
分类号 H01L23/48;H01L23/538;H01L23/528;H01L23/532;H01L21/768;H01L29/06;H01L23/522 主分类号 H01L23/48
代理机构 Eschweiler & Potashnik, LLC 代理人 Eschweiler & Potashnik, LLC
主权项 1. An integrated circuit, comprising: a conductive body disposed over a substrate and having tapered sidewalls that cause an upper surface of the conductive body to have a greater width than a lower surface of the conductive body; a projection disposed on and in contact with the upper surface of the conductive body and having tapered sidewalls that extend from the upper surface of the conductive body to an upper surface of the projection, wherein the tapered sidewalls cause a bottom of the projection to have a width that is greater than a width of the upper surface of the projection and that is smaller than a width of the upper surface of the conductive body; and a dielectric material surrounding the conductive body and the projection.
地址 Hsin-Chu TW