发明名称 Three dimensional integrated circuit structure and method of manufacturing the same
摘要 Provided is a three dimensional integrated circuit structure including a first die, a through substrate via and a connector. The first die is bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is embedded in the first passivation layer. The through substrate via penetrates through the first die and is electrically connected to the second die. The connector is electrically connected to the first die and the second die through the through substrate via.
申请公布号 US9633917(B2) 申请公布日期 2017.04.25
申请号 US201514830740 申请日期 2015.08.20
申请人 Taiwan Semiconductor Manufacturing Co., Ltd. 发明人 Tsai Wen-Ching;Chen Ming-Fa;Yu Chen-Hua
分类号 H01L25/065;H01L21/66;H01L23/31;H01L23/538;H01L23/00;H01L25/00;H01L21/56;H01L21/82 主分类号 H01L25/065
代理机构 Jianq Chyun IP Office 代理人 Jianq Chyun IP Office
主权项 1. A three dimensional integrated circuit structure, comprising: a first die bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is formed in the first passivation layer and extending to the first dielectric layer; first redistribution lines embedded in the first dielectric layer; a through substrate via penetrating through the first die and electrically connected to the second die; and a connector electrically connected to the first die and the second die through the through substrate via.
地址 Hsinchu TW