Process for integrated circuit fabrication including a liner silicide with low contact resistance

摘要

An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.

主权项

1. A process, comprising:
forming a source region and a drain region for a transistor from a semiconductor material; depositing a high dopant concentration delta-doped layer on a top surface of the source region and drain region; depositing an overlying a pre-metal dielectric layer; forming a set of openings extending through the pre-metal dielectric layer to expose the high dopant concentration delta-doped layer on the top surface of the source region and drain region; depositing a metal at the bottom of the set of openings in contact with the high dopant concentration delta-doped layer; and heating to initiate a salicidation reaction of the metal and at least a first portion of the high dopant concentration delta-doped layer to form a silicide region on the source and drain regions.