PROGRAMMABLE SEQUENTIAL LOGIC

摘要

1301131 Integrated circuits TEXAS INSTRUMENTS Inc 7 April 1970 [30 April 1969] 16461/70 Heading H1K [Also in Division H3] A set of logic gates T 11 to T nm , further logic gates Q 11 to Q mk , and a binary store are all formed on the same semi-conductor substrate. The FET's are all formed from orthogonal diffusions in a common substrate, Fig. 3, one diffused strip 30 forming the drains of T 11 to T n1 , another 32 the drains of T 11 to T n1 , another 32 the drains of T 12 to T n2 and another 36 the sources of both T 11 to T n1 and T 12 to T n2 . An insulating layer carrying metal electrodes is made thin at the gate region of those FET's which are required to be full formed, (e.g. T 11 , T 31 , T 42 &c.) and thick at the other. Each column T 11 to T n1 , T 12 to T n2 &c. constitutes a NAND or NOR gate depending upon the polarity of the logic used and of the channels; and each row Q 11 to Q m1 , Q 2 to Q m2 &c. likewise forms a NAND or NOR gate. The selective formation of the FET's predetermines the logical sums and products, and the storage flip-flops (18, Fig. 1, not shown) feed back to selected inputs (I) to enable so-called sequential logic to be effected. A shift register (20) may be included and buffer stages (22) are provided.