发明名称 DELAY DIVIDER CIRCUIT
摘要 PURPOSE:To reduce elements in number by separately setting the delay time of each drain of a multi-drain element. CONSTITUTION:Among output drains D3, D4 and D6 of flip-flop FF, the delay time of drain D6 is made longer than those of other D3 and D4 by time Ti. Here, drain D6 is arranged away from an injector and the gate is made into a thin and long channel, so that the delay time can be controlled. Using this time Ti makes it possible to constitute a delay divider circuit together with the gate circuit connected to FF without using a delay element.
申请公布号 JPS5530287(A) 申请公布日期 1980.03.04
申请号 JP19780104219 申请日期 1978.08.25
申请人 SEIKO INSTR & ELECTRONICS 发明人 ARAI SATOSHI
分类号 H03K23/58;H03K21/00;H03K23/64;(IPC1-7):03K23/30 主分类号 H03K23/58
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