发明名称 TAP CONTROL CIRCUIT OF INDIVIDUAL WRITEEIN RAM SYSTEM
摘要 PURPOSE:To reduce the cost, by processing the amount of tap control into a plurality of RAM's as the bit pattern, in the tap control circuit for transversal type equalizer. CONSTITUTION:The amount of tap control is stored in RAM's 21-1-21-n to each tap as the bit pattern and the data are read out in the order designated at the readout address counter 22 normally. The control data generating circuit 24 discriminates the level of signal input and inputs the renewal control data each tap to each RAM, and the signal of write-in start is outputted to the write-in counter 25. When the addresses of the counters 25, 22 are in agreement with each other at the write-in period designation circuit 26, the designation during write-in period is made to the readout/write-in control circuit 27. The circuit 27 instructs the production of write-in pulse to the write-in pulse generation circuits 28-1-28-n, and the circuits 28-1-28-n compare the content read out from RAM with the renewal data to RAM from the circuit 24, if they are different, the write-in pulse is produced and the write-in data is written in RAM.
申请公布号 JPS55104116(A) 申请公布日期 1980.08.09
申请号 JP19790011297 申请日期 1979.02.02
申请人 FUJITSU LTD 发明人 TOKIMASA SATORU;YAMAZAKI KIYOHIRO;TANIGUCHI TOORU
分类号 H03H15/02;H04B3/04;(IPC1-7):03H15/02 主分类号 H03H15/02
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