| 摘要 |
PURPOSE:To shorten the time of design by making it possible to perform the multiplication of a binary numeral expressed by the complement display of 2 by adding a gate that inverts or does not invert a multiplicand and further by adding a gate to only the unit circuit of the final stage so that four-input addition can be performed. CONSTITUTION:When the multiplication of a binary numeral by the complement display of 2 is performed on the basis of algorithm (table 50) of Booth, this algorithm performs the multiplication by the arithmetic of three kinds of numbers [(0,1), (1,0) and (0,0).(1,1)] of combination (Yn,Yn-1) of two adjacent bits of multiplier Y input in series, but since the 2nd arithmetic of (1,0) is subtraction, a conventional series-parallel multiplier can not perform the arithmetic. For the purpose, the conventional series-parallel multiplier has all unit circuits 15 (TM-T2) provided with additional gates that invert a multiplicand by control signal YS18 and a circuit for ''1'' input needed for subtraction is added to unit circuit 16 of the final stage corresponding to the lowest-order digit of the multiplicand so as to perform the subtraction by four-input addition of the partial product, multiplicand, carry and ''1'' input. |
