发明名称
摘要 <p>PURPOSE:To enable high speed operation, by using the double balance type circuit connecting the output side of the differential amplifier of two current switch type in parallel and driving the memory with the logical sum of the differential amplifier outputs consisting of the selection signal and write-in and readout signal.</p>
申请公布号 JPS5617755(B2) 申请公布日期 1981.04.24
申请号 JP19760109228 申请日期 1976.09.10
申请人 发明人
分类号 G11C11/41;G11C11/411;G11C11/414 主分类号 G11C11/41
代理机构 代理人
主权项
地址