| 摘要 |
PURPOSE:To contrive the device high speeding and low powering by a method wherein on a substrate having a semiconductor layer detacted by an isolator CMOSFET are integrated and an n channel is made of a p type lower layer and an n-or-p type upper layer, while a p channel is made of an n type lower layer and an n-or-p type upper layer. CONSTITUTION:On an Si island on a sapphire substrate 1 MOSFET Qn and Qp of an n channel and a p channel are formed. The layers 51, 52 are sources and the layers 61, 62 are drains. On the channels the n type polymer Si gate electrodes are formed through the films oxide 31, 32. The n channel is made of a deep p layer (the first layer) part and a shallow p layer (the second layer) part, while the p channel is made of a deep n layer (the third layer) part and a shallow p layer part. The second, fourth layers together with the first, third layers determine the threshold value voltage selecting either the n type or p type according to the work function of the gate material. These first - fourth layers are formed through the ion double injection. Through said constitution the C-MOS device works with small power consumption and high speed. |
