| 摘要 |
PURPOSE:To enable data writing in nibble mode under single mode state equivalently by performing writing in a memory element in nibble mode when clock is given continuously and generating a timing signal for starting the memory element and a timing signal that set data in the memory element as a set when clock is given singly. CONSTITUTION:In a continuous mode, operation is made in a nibble mode by toggling a CAS signal to one RAS signal by a timing generating circuit 17. In the case of a single mode, writing of data is made by generating a set of RAS signal and CAS signal from a timing generating circuit 17 basing on output of a counter 16 of number of times of data transfer for each time memory starting signal MD is received by switching the counter 16 of number of times of data transfer and timing generating circuit 17 by a switching signal from a single mode discriminating circuit 15. At this time, address of the second and succeeding data is obtained by stepping an address counter 18 by output of the counter of number of times of data transfer. |
