| 摘要 |
PURPOSE:To obtain a bit phase synchronizing circuit which has less errors by detecting change points of a digital data signal and a device clock, and selecting a digital signal read-in clock to a 0 and a pi phase and synchronizing it with the device clock. CONSTITUTION:A bit phase asynchronous input signal 17 and the device clock 18 are supplied to change point detecting circuits 10 and 11 to detect their rising and falling change points. Two change point detection results 19 and 20 are sent to change point coincidence detecting circuits 12 and 13 to detect information 21 on the coincidence between the rising of the clock and change point of the input signal and information 22 on the coincidence between the falling of the clock and change point of the input signal; and those pieces of information are sent to a control circuit 14 respectively. The circuit 14 selects a clock which is pi phase to the clock at the time of the signal 21 and a clock which is 0 phase to the clock at the time of the signal 22. Then the input signal is read in a buffer memory 15 by the read-in clock 18 selected by the circuit 14, synchronized in a buffer memory 16 by the device clock, and used as device data 23. |
