发明名称 |
COLUMN IV TRANSISTORS FOR PMOS INTEGRATION |
摘要 |
Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures. |
申请公布号 |
US2016372547(A1) |
申请公布日期 |
2016.12.22 |
申请号 |
US201615255902 |
申请日期 |
2016.09.02 |
申请人 |
INTEL CORPORATION |
发明人 |
GLASS GLENN A.;MURTHY ANAND S. |
分类号 |
H01L29/06;H01L23/535;H01L29/36;H01L29/417 |
主分类号 |
H01L29/06 |
代理机构 |
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代理人 |
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主权项 |
1. A integrated circuit device, comprising:
a substrate having a fin extending therefore, the fin including a channel region; a gate electrode over the channel region; and source and drain regions formed at least one of on and in the fin and adjacent to the channel region, each of the source and drain regions having a total thickness comprising a p-type liner of silicon or germanium or silicon germanium and a p-type cap having a germanium concentration in excess of 80 atomic %, wherein the liner is less than 50% of the total thickness. |
地址 |
Santa Clara CA US |