发明名称 HIGH-SPEED MULTIPLITER
摘要 PURPOSE:To speed up a multiplier by inputting two numeral data consisting of the combination of binary values and carry information, multiplying respective parts, adding the multiplied results, and then outputting the added results as a binary value and carry information. CONSTITUTION:A value A set in a multiplied register 6 and respective bits of a multiplying register 8 are respectively inputted to a circuits 91-93 for obtaining secondary booth algorithm or a circuit 10 for obtaining modified secondary booth algorithm to find out partial products, which are inputted to an adder 12. Partial products between a value (a) of a carry information register 7 and respective bits in the multiplying register 8 are found out by an one-bit multiplier 11 and inputted to the adder 12. Since data having a similar format to the output of a carry holding adder can be used as I/O data, the addition of carries may be executed only at the final time of a series of arithmetic processing and the multiplying processing can be speeded up.
申请公布号 JPS60142424(A) 申请公布日期 1985.07.27
申请号 JP19830250029 申请日期 1983.12.28
申请人 FUJITSU KK 发明人 TAKEBAYASHI TOMOYOSHI;UMIGAMI SHIGEYUKI
分类号 G06F7/53;G06F7/508;G06F7/52;G06F7/527;G06F7/533 主分类号 G06F7/53
代理机构 代理人
主权项
地址