发明名称 INSPECTION SYSTEM FOR LOGIC CIRCUIT
摘要 PURPOSE:To enable normal inspection, by adding signals for scan-in, scan-out and scan address in a sharing test system and an output signal selector for a random number generator, a code analyzer and a counter in the self test system. CONSTITUTION:In the test mode 1 of a sharing test system, signals for scan-in, scan-out and scan address are added. Here, the scan address is selected to sent a scan lock thereby allowing the taking of system data without sending system clock. This mechanism enables the taking of system data on the output side FF without breaking the value scanned into the input side FF precisely the same in the phase. In the test mode 2 of a self test system, a mechanism for selecting output signals of a random generator, a code analyzer and a counter are added to all of FFs in circuits to operate all the FFs in the same phase thereby permitting the taking of system data simultaneously. This guarantees a stabilized inspection in the two test modes.
申请公布号 JPS61212777(A) 申请公布日期 1986.09.20
申请号 JP19850052212 申请日期 1985.03.18
申请人 HITACHI LTD 发明人 NISHIDA TAKAO;HIYAMA TORU;ISHIYAMA TAKASHI;MIYAMOTO SHUNSUKE
分类号 H03K19/00;G01R31/28;G01R31/3185 主分类号 H03K19/00
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