| 摘要 |
<p>A novel memory system is disclosed which utilizes pipelining techniques to read data from a memory array (30a, 30a1 ) and to write data to a memory array. More data may be read from the novel memory system (40), within a unit of time, relative to the amount of data which may be read from a conventional memory system during the unit of time. The novel memory system includes latch circuits (40a-c) interposed between the row decoder (30b) and the row driver, between the row driver (30c) and the memory array, between the memory array and the column sense amplifiers, and between the column sense amplifiers (30g) and the column multiplexer - (30f). The same number of latch circuits (40e-h) are interposed in serial fashion between the incoming row and column address bus and the column multiplexer. Consequently, as a result of the use of these latch circuits in a memory system, pipelining techniques are utilized in the memory system for the improvement of the performance of the memory system.</p> |
