Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM

摘要

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a core comprising:
a front end unit;a plurality of register files coupled to the front end unit, the plurality of register files associated with a plurality of threads;a plurality of register sets coupled to the front end unit, each of the plurality of register sets associated with one of the plurality of threads and including a first register to store an indicator to indicate whether the processor is enabled to store an active state of one of the plurality of threads stored in one of the plurality of register files in a storage unit of the processor on entry to a system management mode (SMM) or to a system management random access memory (SMRAM) coupled to the processor; anda plurality of execution units to execute instructions; and the storage unit to store the active state when the processor is in the SMM.