| 摘要 |
<p>In a signal processor for processing zeroth through (N - l)-th input signal elements into zeroth through (N - l)-th output signal elements, the input elements are initially stored, as memorized data, in respective memory addresses of a memory arrangement (ll, l2) by a memory accessing arrangement which comprises a first address calculating arrangement (3ll, 32l) for calculating a first address for the memory addresses. A distance indicating arrangement (3l2, 322) is for indicating an address distance from the first address among the memory addresses. By using the first address and the address distance a second address is calculated by a second address calculating arrangement (3l3, 323). A pair of memorized data are read from the first and the second addresses as a pair of read data. A calculation performing circuit (20) is for performing a predetermined calculation on the pair of read data by using a coefficient read from a read-only memory (l4) to produce a pair of calculated data which are stored in the first and the second addresses as the memorized data. The calculation performing circuit performs the predetermined calculation a plurality of times to produce the output elements. </p> |
