Packet switch suitable for integrated circuit implementation.

摘要

The invention relates to a packet switch for exchanging packets received over a plurality of input lines (200) and outputting exchanged packets, to a plurality of output lines (213), comprising: multiplexing means (202) for time-division multiplexing the packets received over said plurality of input lines to multiplexed packets; address detecting means (204) for detecting an address of each packet in the multiplexed packets to produce a destination address; write address generating means (104) responsive to the destination address for generating write address; read address generating means (105) for sequentially generating read addresses; memory means (103) constituted by a plurality of memory areas individually associated with said plurality of output lines, said memory means responsive to said write address for storing each packet of the multiplexed packets in any of said memory areas, and responsive to said read addresses for producing exchanged multiplexed packets by reading the stored packets; and demultiplexing means (212) for demultiplexing said exchanged multiplexed packets into said exchanged packets and delivering them to said plurality of output lines.