| 摘要 |
PURPOSE:To reduce the irregularity of the cycle of an input signal by connecting a multiplier and a frequency divider between the input signal and a counter and making the output of the frequency devider a gate signal. CONSTITUTION:An input signal 11 is multiplied by (n) by a multiplier 1 and the output of the multiplier 1 is divided into 1/m in its frequency by a frequency divider 2. The output of the frequency divider 2 is supplied to a counter 3 as a gate signal 12 while he counter 3 opens and closes a gate following the gate signal 12 to count a reference clock 13 only during a gate open time. This count value becomes count data 14 as the output of the counter 3 to make it possible to reduce not only the irregularity of a gate time but also the cycle irregularity of the input signal. |
