Decision feedback equalizer

摘要

A decision feedback equalizer for N-level amplitude modulated signal, includes: (N−1) level conversion circuits to add (N−1) shifting voltages to the amplitude modulated signal respectively; (N−1)×N determination feedback equalization-correction circuits to perform N types of decision feedback equalization processing, each of which adding each of N-level offset voltages corresponded to any one of N levels of a reception data ahead of one data cycle, on each of the (N−1) level shifted signals to generate (N−1) sets of N equalization correction signals; (N−1)×N comparison circuits; (N−1)×N first latch circuits; (N−1) selection circuits to select a comparison result of the N comparison circuits in each (N−1) sets; (N−1) second latch circuits; and a decoder, wherein each of the (N−1) selection circuits selects an equalization-correction signal among the N equalization-correction signals in each (N−1) set according to outputs latched by the (N−1) second latch circuits.

主权项

1. A decision feedback equalizer for N-level amplitude modulated signal of a reception data, wherein N is an integer of 4 or more, the decision feedback equalizer comprising:
(N−1) level conversion circuits configured to add (N−1) shifting voltages to the N-level amplitude modulated signal respectively to generate (N−1) level shifted signals; (N−1)×N determination feedback equalization and correction circuits configured to perform N types of decision feedback equalization processing, each of which adding each of N-level offset voltages corresponded to any one of N levels of the reception data ahead of one data cycle, on each of the (N−1) level shifted signals to generate (N−1) sets of N equalization correction signals; (N−1)×N comparison circuits configured to compare the N equalization correction signals in each of the (N−1) sets with a reference voltage; (N−1)×N first latch circuits configured to latch comparison results of N comparison circuits in each of the (N−1) sets; (N−1) selection circuits configured to select a single comparison result among the comparison results of the N comparison circuits in each of the (N−1) sets, wherein the (N−1) selection circuits are arranged in at least a first stage and a second stage for selecting the single comparison result; (N−1) second latch circuits configured to latch outputs of the second stage of (N−1) selection circuits; and a decoder configured to decode the outputs of the (N−1) second latch circuits to determine output data having N levels, wherein each of the (N−1) selection circuits is configured to select an equalization correction signal among the N equalization correction signals in each of the (N−1) sets according to outputs latched by the (N−1) second latch circuits.