| 摘要 |
<p>A semiconductor memory device has a plurality of memory cells (351,352,353,354) in an array, into which the memory cells (351,352,353,354) data is writable, and which can subsequently be read. Each memory cell has a switching element (111) with one terminal connected to a bit line (120) of the array another terminal connected to at least one ferroelectric capacitor (112,113,114,115), and a control terminal connected to a word line (121). The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor (427) and a capacitor (428) other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality (112,113,114,115) of ferroelectric capacitors are connected to the switching element, so that different data are writable into each. <IMAGE></p> |
