| 摘要 |
The DATA signal output (1) is connected to the status word register (6) and the display driver (8). The clock signal CL output (2) is connected to the clock signal switch (4). The SEL SW status word selection signal output (3) is connected to the clock signal switch (4), trigger circuit (5), time multiplex register (7) and switching element group switch (9). The clock signal switch (4) is further connected to the status word register (6), time multiplex register (7) and the display driver (8). The trigger circuit (5) is further connected to the time multiplex register (7). The status word register (6) is further connected to the display driver (8) and switching element group switch (9). The time multiplex register (7) is further connected through the switching elements (11, 12...1n, 21, 22...2n,..., m1, m2 ... mn) to the switching element group switch (9). The time multiplex register (7) output (741) is connected to the reset input (51) of the trigger circuit (5). The data output (93) switching element group switch (9) is connected to the DATA signal input (10). In order to interconnect the control section with the microprocessor at a shorter distance it is possible to merge the DATA signal output (1) and DATA signal input (10) in one two-way data cable.<IMAGE>
|
