| 摘要 |
The device displays a 24 bit color of high resolution by a 4 divider of 64Mhz DOTCLK to realize a 1024 x 768 resolutions. The circuit includes a clock generation unit (40) which has a 1st flip flop (61) to 2-divide DOTCLK signal and a 2nd flip flop (62) to 4-divide signal and 3rd-5th flip flops (63-65) to delay clock signal, a control signal generator (50) which produces control signals (RAS0-RAS3) to control a memory bank of VRAM and which has a row address (81), a column address (82), and a state code (83).
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