| 摘要 |
<p>A clock recovery circuit 10 for a data processing system 2 generates a clock signal which does note require a preamble for synchronization. The circuit has two burst oscillatores 22 and 24, and multiplexer 26 and a phase lock loop 30. The two burst oscillators respond to translations in the incoming NRZ signal and accordingly output a clock signal. The phase lock loop controls the oscillation rates of each of the burst oscillatores. The multiplexer controls which burst oscillator is used as the clock signal for a shift register which stores the incoming data. <IMAGE></p> |
