| 摘要 |
A clock reproducing circuit which can generate a good demodulation signal by detecting the timing point of the demodulation in an extremely short period of time; a digital demodulator which uses this clock reproducing circuit; a device for estimating a bit error rate of which deterioration of communication efficiency is limited to the extremity; and an AFC circuit which is capable of correcting a frequency drift in the correct direction exactly even when the frequency drift is great. The digital demodulator demodulates a signal detected by detecting a modulated wave by a given detector in accordance with timing clock signals. The demodulator comprises means for detecting the correlation of every two extraction points adjacent to each other by sampling a signal in the process of demodulation at a plurality of extraction points predetermined for every unit data cycle (symbol cycle); means for comparing the sizes of the correlations detected by the correlation detecting means, determining two pairs of extraction points of the greatest and second greatest sizes of correlation, and generating timing clock signals in accordance with the determination; and means for shifting the phase of signal in the process of demodulation in order to equalize the correlation sizes detected by the two pairs of the extraction points. The device for estimating a bit error rate detects the correlation of every two extracted points adjacent to each other by sampling a signal in the process of demodulation at a plurality of extraction points predetermined for every unit data cycle (symbol cycle), and estimates the bit error rate in accordance with the distribution of the detected correlations. Furthermore, in the AFC circuit, the frequency drift of the modulated wave is corrected by comparing the bit error rate estimated by the said bit error estimating device and the measured bit error rate. |
