Address modulo adjust unit for a memory management unit for monolithic digital signal processor

摘要

A memory management unit suitable fo use in a digital signal processor having internal and eternal memories is described. The unit is especially designed to facilitate numeric algorithms such as fast fourier transforms, auto-correlation and digital filtering by relieving the programmer from the need to monitor memory accesses. Automatic post-updating of memory addresses is provided after indirect memory references. Also, memory boundary-checking is performed according to a user-specified modulus value, and a memory reference is automatically adjusted to fall within the user-specified address range. A dual-access register file stores initial memory addresses and their associated modulus values and in a dual-bus embodiment a pair of address generation units provides post-updates of the addresses stored in the register files. Direct addressing of memory is also supported by the memory management unit and a page register internal to the unit allows the user to specify memory page information during a direct address operation. A modulo-adjust portion of the address generation unit implements any user-specified modulii in the range 0 to 64, as well as modulii of 128, 256 and 512. A method of operating a memory management unit to provide the features obtained by the instant invention is also described.