| 摘要 |
The bit line sense amplifier is controlled according to characteristics of word lines and bit lines by adopting self time bitline sense amplifier control scheme. The DRAM includes a row line decoder(2) connected to a memory array(4) through a word line driver(3) and word line(WD), a bit line sense amplifier(6) for detecting and amplifying data transmitted through bit lines(BL), and a sense amplifier controller(100) connected to a memory array(4), a bit line sense amplifier driver(5), row decoder(2) and a word line driver(3) to control the driving timing of the bit line sense amplifier according to characteristics of the bit lines and word lines.
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