Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure

摘要

A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.

主权项

1. An LDMOS transistor fabricated on a semiconductor substrate, the transistor comprising:
a well region located in the semiconductor substrate and having a first conductivity type; a base oxide layer located on an upper surface of the semiconductor substrate over a first portion of the well region; a gate dielectric structure including a shallow field oxide region having a birds beak profile extending below the upper surface of the semiconductor substrate over a second portion of the well region; a gate electrode including a first portion disposed over the base oxide layer and a second portion disposed over a portion of the gate dielectric structure; a drift implant formed by a diffused dopant having the first conductivity type and disposed in the well region below the gate dielectric structure; and a surface field implant formed by a diffused dopant having a second conductivity type and disposed in the well region below the drift implant, wherein the drift implant and the surface field implant are self-aligned to the gate dielectric structure such that opposing edges of the gate dielectric structure are substantially aligned with corresponding outer boundary edges of the drift implant and the surface implant.