发明名称 Non-volatile semiconductor memory and data erasing method for the same
摘要 The non-volatile semiconductor memory disclosed includes an X-decoder and word line potential supply circuits, and a current setting/holding circuit. The X-decoder and the word line potential supply circuits set all word lines ground potential in the flash erasing operation, to a predetermined first over-erasing judgment reference potential in an "on" cell detecting operation, and to a predetermined second over-erasing judgment reference potential for judgment of over-erasing deeper than the first over-erasing judgment reference potential and, in an "on" cell specifying operation, set predetermined selected word lines to the first over-erasing judgment reference potential while setting other word lines than the selected word line to the second over-erasing judgment reference potential. The current setting/holding circuit sets the reference current in an "on" cell specifying reference current setting operation such that the result of the check by a sense amplifier is "on". It is possible to eliminate the possibility of generation of a memory cell transistor in a non-erased state, thus ensuring quick operation.
申请公布号 US5657272(A) 申请公布日期 1997.08.12
申请号 US19960617289 申请日期 1996.03.18
申请人 NEC CORPORATION 发明人 SATO, TOSHIYA
分类号 G11C17/00;G11C16/02;G11C16/06;G11C16/34;(IPC1-7):G11C11/34 主分类号 G11C17/00
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