发明名称 Automatic gain control circuit
摘要 Analog input signals are supplied to a full-wave rectifier (1) and the peak output of the circuit (1) is held by means of a peak holding circuit (2). A comparator (3) compares the peak output with a reference signal VREF, and the comparator output operates a switch (7). Namely, when the output level of the circuit (2) is lower than the level of the signal VREF (linear amplifying area), one contact (c) of the switch (7) is connected so that the output of a fixed gain delay circuit (6) is outputted as the gain-controlled signal and, when the output level of the circuit (2) is higher than the level of the signal VREF (AGC area), the other contact (d) of the switch (7) is connected so that the output of a VCA circuit (5) is outputted as the gain-controlled signal.
申请公布号 AU4547296(A) 申请公布日期 1997.08.22
申请号 AU19960045472 申请日期 1996.01.31
申请人 ASAHI KASEI MICROSYSTEMS CO., LTD.;NIPPON TELEGRAPH AND TELEPHONE CORPORATION 发明人 TOMOKAZU TAKASAKI;KAZUHIRO DAIKOKU;KENJI YAMADA
分类号 H03G1/00;H03G3/30 主分类号 H03G1/00
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