| 摘要 |
An apparatus and method for reducing spurious sidebands in the tuning signal of phase locked loop frequency synthesizers and phase locked loops is disclosed. A frequency synthesizer comprises an oscillator, a divider, a difference circuit and a sampling circuit. The oscillator produces a variable frequency oscillator signal in response to an applied tuning signal. The divider circuit has a division factor and communicates with the oscillator to receive and divide the variable frequency oscillator signal by the division factor to produce a reduced frequency signal. The difference circuit communicates with the divider circuit to receive the reduced frequency signal and produce a difference signal. The difference signal corresponds to the phase difference between the reference signal and the reduced frequency signal. The sample circuit intermittently samples the difference signal in response to timing signal to produce a tuning signal which approaches a DC characteristic. The tuning signal serves to adjust the oscillator frequency in a direction to diminish phase differences in the reference signal and the reduced frequency signal. In another aspect of the invention, a PLL is disclosed with the sampling circuitry for intermittently sampling the difference signal in response to a timing signal. |
