| 摘要 |
A semiconductor memory device comprises full-CMOS type memory cell which device can shorten read time and write time of storage information. The memory cell thereof comprises one pair of load transistors, one pair of driving transistors, and one pair of transferring transistors which pair of transistors constitute a flip-flop circuit respectively. In the memory cell, a first pair-of-bit-lines is connected to source/drain side of the pair of transferring transistors, while a second pair-of-bit-lines is connected to source side of the pair of driving transistors. At the read time, signal from the four bit lines is inputted to a sense amplifier, while at the write time, a complementary signal based on write information is applied to both of the first pair-of-bit-lines and the second pair-of-bit-lines from a write buffer.
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