| 摘要 |
PROBLEM TO BE SOLVED: To provide a register access circuit and a data processing method using this register access circuit for realizing the parallel processing of a CPU and an LSI and the high speed transfer of data without making the instruction word length of the CPU coincide with the bus with width of the LSI, or providing any inside bus width changeover switch, or taking any countermeasure at the software side of the CPU. SOLUTION: A register access circuit 201 is provided with data input terminals 1e01-1e32, 32 pieces of first stage flip flops 1a01-1a32, 16 pieces of second flip flops 1b01-1b16 connected with the first stage flip flops 1a01-1a16, OR gate 1g, flip flop 1h, NAND gate 1i, 16 data selector circuits 1c01-1c16, 32 gate circuits 1d01-1d32, and 32 data output terminals 1f01-1f32. This register access circuit is connected through an interruption requesting circuit with the CPU circuit.
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