发明名称 PROCESSOR AND COMPILER AND COMPILE METHOD AND RECORDING MEDIUM
摘要 PROBLEM TO BE SOLVED: To solve the problem that performance is deteriorated due to impossibility to facilitate a countermeasure to a flow at the time of execution resulted from the static decision of execution units, and that it is difficult to facilitate a countermeasure to the extension of hardware such as the improvement of parallelism in a processor on the condition of static parallel scheduling such as a VLIW system. SOLUTION: Instruction constituting elements are provided with plural parallel execution boundary information A10 and B11. The parallel execution boundary information for each execution flow is set, and selected and referred according to the execution flow. Also, each parallel execution boundary information is provided with information specified for certain parallelism or the information of only inter-instruction dependency, and they are switched and used so that it is possible to facilitate a countermeasure to the extension of hardware.
申请公布号 JP2001236227(A) 申请公布日期 2001.08.31
申请号 JP20000047146 申请日期 2000.02.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HEIJI TAKEHITO
分类号 G06F9/38;G06F9/32;G06F9/45;(IPC1-7):G06F9/38 主分类号 G06F9/38
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