发明名称 PLL FREQUENCY SYNTHESIZER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To perform switching between a variable mode and a fixed mode and to set the frequency division ratio of a reference counter for a PLL frequency synthesizer circuit. SOLUTION: This PLL frequency synthesizer circuit, which is provided with a crystal oscillator 20, the reference counter 33, a voltage controlled oscillator 30, a programmable counter 27, a loop filter 29 and a phase comparator 28, outputs the output signal of the oscillator 30 and has a mode changeover switch 7 that selects either or both modes between the fixed mode in which a desired piece of frequency division ratio data among pieces of frequency division ratio data stored in a counter value holding circuit 2 is inputted to both the counters 27 and 33, and the variable mode in which frequency division ratio data outputted from a shift register 26 is inputted to either or both counters 27 and 33.
申请公布号 JP2001285061(A) 申请公布日期 2001.10.12
申请号 JP20000100232 申请日期 2000.04.03
申请人 SHARP CORP 发明人 TOYOOKA TAMOTSU;YOSHIZAWA TASUKU
分类号 H03L7/183;(IPC1-7):H03L7/183 主分类号 H03L7/183
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