CALCULATION METHOD FOR DELAY TIME OF MULTI-VALUED LOGIC

摘要

PROBLEM TO BE SOLVED: To reduce execution time of a circuit simulation necessary to calculate delay time of multi-valued logic. SOLUTION: In a calculation method for delay time of multi-valued logic, among logic varying patterns obtained from a truth table of notable cells, patterns varying at one level in an input logic are stored into a pattern file 4 for execution of circuit simulation and patterns varying at more than one level in the input logic are stored into a pattern file 5 for non-execution of circuit simulation. A delay parameter file 6 is created by performing the circuit simulation in a variety of conditions for the patterns in the file 4 and a transcribed data file 7 for display parameter is created by describing from the file 6 for the patterns in the file 5. A display library 8 is created from the file 6 and file 7, delay times of the cells in a specific condition are calculated by interpolation through the use of the library 8 to store the calculation result into a delay time file 10.