| 摘要 |
The scalable multi-bit flash memory cell includes three regions: the first-side region, the gate region, and the second-side region, in which the gate region includes two stack-gate transistors and one select-gate transistor. The first-side/second-side region comprises a sidewall-oxide spacer formed over the gate region and from top to bottom comprises a planarized thick-oxide layer, a silicided conductive layer formed on a flat bed, and a common-diffusion region. The stack-gate transistor comprises from top to bottom a sidewall dielectric spacer, an elongated control-gate layer formed over an intergate dielectric layer, and an integrated floating-gate layer. The select-gate transistor comprises a planarized conductive island formed over a gate-dielectric layer and is connected to a word line. A plurality of scalable multi-bit flash memory cells are alternately arranged to form a scalable multi-bit flash memory cell array.
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