RECEIVING CIRCUIT, METHOD FOR ADJUSTING RECEIVING CIRCUIT TIMING, AND SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To reduce read data errors.SOLUTION: A control signal generating circuit 35 of a receiving circuit 24 generates an enable signal EN1 on the basis of a delay strobe signal DQSd, and generates an enable signal EN2 on the basis of a transfer setting value FSP, a read control signal RCNT, and a core clock signal CKc. A pattern signal generating circuit (PG) 36 generates determination pattern data TD on the basis of the enable signal EN1. An asynchronous transfer circuit 37 latches the determination pattern data TD on the basis of the enable signal EN1 and the delay strobe signal DQSd, and outputs determination data CT on the basis of the enable signal EN2 and the core clock signal CKc. A determining circuit 38 determines a generation timing of the enable signal EN2 based on the transfer setting value FSP on the basis of the determination data CT. A setting value calculating circuit 39 calculates the transfer setting value FSP on the basis of the determination results of the determining circuit 38.SELECTED DRAWING: Figure 1