发明名称 |
ELECTRODE STRUCTURE FOR USE IN AN INTEGRATED CIRCUIT |
摘要 |
A memory cell, comprising:
a first layer (202) of conductive material;
a dielectric layer (204) formed on a surface of the first layer;
an opening (206) formed in the dielectric layer to expose a portion of the surface of the first layer;
a binding layer (210') formed on the dielectric layer and on the exposed portion of the surface of the first layer;
a second layer (212) of conductive material formed on the binding layer;
a layer (214) of doped chalcogenide material formed on the second layer of conductive material; and
a third layer (216') of conductive material formed on the layer of doped chalcogenide material. |
申请公布号 |
EP1446832(A2) |
申请公布日期 |
2004.08.18 |
申请号 |
EP20020797134 |
申请日期 |
2002.11.19 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
MOORE, JOHN, T.;BROOKS, JOSEPH, F. |
分类号 |
H01L21/3205;H01L21/768;G11C13/00;G11C13/02;H01L23/485;H01L23/52;H01L27/105;H01L27/24;H01L45/00 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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