发明名称 |
DUAL BANK SYSTEM, MEMORY USED IN THE SYSTEM, AND ON-DIE TERMINATION METHOD OF THE MEMORY, IN WHICH LEAKAGE CURRENT IS REDUCED |
摘要 |
PURPOSE: A dual bank system and a memory used in the dual bank system and an on-die termination method of the memory are provided to reduce a leakage current through an on-die termination circuit of the memory. CONSTITUTION: A memory used in the dual bank system comprises a command decoder(30), OR gates(OR1,OR2) and an on-die termination(ODT) control signal generation unit(32). The command decoder generates a write signal(WE) and a dummy write signal(DWE) and a dummy read signal(DRD) and a read signal(RD) by decoding command signals(clk,csb,rasb,casb,web) applied from the external. The OR gate(OR1) generates an on-die termination enable signal(ODTEN) by an OR logic operation of the write signal and the dummy write signal. The OR gate(OR2) generates an on-die termination disable signal(ODTIS) by an OR logic operation of the dummy read signal and the read signal. The ODT control signal generation unit enables an on-die termination control signal(PODT) in response to the on-die termination enable signal, and disables the on-die termination control signal in response to the on-die termination disable signal.
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申请公布号 |
KR20040098147(A) |
申请公布日期 |
2004.11.20 |
申请号 |
KR20030030350 |
申请日期 |
2003.05.13 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
JANG, SEONG JIN;JUN, YEONG HYEON;KWAK, JIN SEOK |
分类号 |
G11C5/06;G11C7/10;(IPC1-7):G11C7/10 |
主分类号 |
G11C5/06 |
代理机构 |
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主权项 |
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地址 |
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