发明名称 Memory defect redress analysis treating method, and memory testing apparatus performing the method
摘要 There are provided a failure repair analyzing and processing method and a memory testing apparatus provided with a failure repair analyzing and processing apparatus using this method, that are capable of reducing a time duration required to perform the failure repair analysis and processing for a multi-bit memory having redundancy structure. A plurality of repair analysis units as well as a common failure analysis memory are provided, and these repair analysis units are concurrently operated in parallel with each other, thereby to carry out respective repair analyses and processings for failure memory cells of plural data bits read out from the failure analysis memory in the plural repair analysis units concurrently and in parallel with each other. As a result, a time duration required to execute the failure repair analysis and processing is shortened.
申请公布号 US6907385(B2) 申请公布日期 2005.06.14
申请号 US20030399082 申请日期 2003.04.11
申请人 ADVANTEST CORPORATION 发明人 YASUI TAKAHIRO
分类号 G11C29/56;(IPC1-7):G01R31/26 主分类号 G11C29/56
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