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发明名称
堆叠式半导体元件之制造方法
摘要
一种堆叠式半导体元件之制造方法,包含有下列步骤:a)在一基板,其上具有一预定之电路布局以及一孔槽,之一侧设置一暂时基层;b)将一第一晶粒容设于该基板之孔槽中,并贴附在该暂时基层上,并利用金线电性连接该第一晶粒与该电路布局;c)将一第二晶粒堆叠于该第一晶粒之上,并利用金线电性连接该第一晶粒与该电路布局;d)设置一隔离层于该基板上以及该孔槽中,藉以包覆该第一晶粒与该第二晶粒,以及e)移除该暂时基层。
申请公布号
TW200537674
申请公布日期
2005.11.16
申请号
TW093112803
申请日期
2004.05.06
申请人
硕达科技股份有限公司
发明人
姚武强;白金泉;黄启榜
分类号
H01L23/50
主分类号
H01L23/50
代理机构
代理人
刘緖伦
主权项
地址
苗栗县竹南镇科义路38号2楼
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