A DATA PROCESSING APPARATUS AND METHOD FOR EXECUTING A STREAM OF INSTRUCTIONS OUT OF ORDER WITH RESPECT TO ORIGINAL PROGRAM ORDER

摘要

A data processing apparatus and method are provided for executing a stream of instructions out-of-order with respect to original program order. At least some of the instructions in the stream identify one or more architectural registers from a set of architectural registers. The apparatus comprises a plurality of out-of-order components configured to manage execution of a first subset of instructions out-of-order, the plurality of out-of-order components being configured to remove false dependencies between instructions in the first subset. The plurality of out-of-order components include a first issue queue into which the instructions in the first subset are buffered prior to execution. A second issue queue is used to buffer a second subset of instructions prior to execution, the second subset of instructions being constrained to execute in order. Issue control circuitry is configured to reference both issue queues in order to determine an order of execution of instructions, and is configured to constrain the order of execution of the first subset of instructions by true dependencies between the instructions in both the first and second issue queues, and to constrain the order of execution of the second subset of instructions by both the true dependencies and the false dependencies between the instructions in both the first and second issue queues. This approach provides improved performance and/or reduced energy consumption.

主权项

1. A data processing apparatus for executing a stream of instructions out of order with respect to original program order, said stream including instructions that identify one or more architectural registers from a set of architectural registers, the data processing apparatus comprising:
a plurality of out of order components configured to manage execution of a first subset of said instructions out of order, said plurality of out of order components configured to remove false dependencies between instructions in said first subset, and said plurality of out of order components including a first issue queue into which the instructions in said first subset are buffered prior to execution; a second issue queue into which a second subset of said instructions are buffered prior to execution, said second subset of instructions being constrained to execute in order; and issue control circuitry configured to reference the first issue queue and the second issue queue in order to determine an order of execution of instructions from both the first and second queues, the issue control circuitry being configured to constrain the order of execution of said first subset of instructions by true dependencies between the instructions in both the first and second issue queues, and to constrain the order of execution of said second subset of instructions by both the true dependencies and the false dependencies between the instructions in both the first and second issue queues.