| 发明名称 | Self-calibrating multi-phase clock circuit and method thereof | ||
| 摘要 | A multi-phase clock circuit includes: a phase tuning circuit configured to receive a primitive N-phase clock including N primitive clocks of the same period but distinct phases and output a calibrated N-phase clock including N calibrated clocks in accordance with a first tuning signal, where N is integer greater than one; a clock multiplexing circuit configured to receive the N calibrated clocks and output a first output clock and a second output clock in accordance with a multiplexing control signal; a time-to-digital converter configured to receive the first output clock and the second output clock and output a digital code; and a calibration controller configured to receive the digital code and output the first tuning signal in accordance with a mode select signal. | ||
| 申请公布号 | US9479150(B1) | 申请公布日期 | 2016.10.25 |
| 申请号 | US201514804582 | 申请日期 | 2015.07.21 |
| 申请人 | REALTEK SEMICONDUCTOR CORPORATION | 发明人 | Lin Chia-Liang (Leon) |
| 分类号 | H03H11/16;H03K5/13;H03K5/135;H03K5/00 | 主分类号 | H03H11/16 |
| 代理机构 | Sughrue Mion, PLLC | 代理人 | Sughrue Mion, PLLC |
| 主权项 | 1. A circuit comprising: a phase tuning circuit configured to receive a primitive N-phase clock comprising N primitive clocks of the same period but distinct phases and output a calibrated N-phase clock comprising N calibrated clocks in accordance with a first tuning signal, where N is an integer greater than one; a clock multiplexing circuit configured to receive the N calibrated clocks and output a first output clock and a second output clock in accordance with a multiplexing control signal; a time-to-digital converter configured to receive the first output clock and the second output clock and output a digital code; and a calibration controller configured to receive the digital code and output the first tuning signal in accordance with a mode select signal. | ||
| 地址 | Hsinchu TW | ||