发明名称 Scheduling threads according to real time bit in predetermined time period or in variable time period of requested time ratio
摘要 A multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, and a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread. The thread scheduler specifies execution of at least one hardware thread pre-selected among the plurality of hardware threads in a predetermined first execution period, and specifies execution of a variably selected hardware thread in a second execution period other than the first execution period. A time ratio between the predetermined first execution period and the second execution period is set according to processing requests.
申请公布号 US9501320(B2) 申请公布日期 2016.11.22
申请号 US201314092498 申请日期 2013.11.27
申请人 RENESAS ELECTRONICS CORPORATION 发明人 Adachi Koji;Miyamoto Kazunori
分类号 G06F9/48;G06F9/38 主分类号 G06F9/48
代理机构 McGinn IP Law Group, PLLC 代理人 McGinn IP Law Group, PLLC
主权项 1. A multi-thread processor comprising: a plurality of hardware threads each of which generates an independent instruction flow; a thread scheduler that outputs a thread selection signal in accordance with a schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle of the thread scheduler among the plurality of hardware threads; and a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread; wherein the thread scheduler specifies execution of at least one hardware thread pre-selected among the plurality of hardware threads in a predetermined first execution period, and specifies execution of a variably in time selected hardware thread in a second execution period other than the first execution period, the first execution period being a period during which a real-time bit signal is a first value, and the second execution period being a period during which the real-time bit signal is a second value, wherein a time ratio between the predetermined first execution period and the second execution period is set according to processing requests, wherein the predetermined first execution period is a predetermined period of time in which the at least one hardware thread pre-selected among the plurality of hardware threads is specified for execution, and wherein the second execution period is a variable period of time in which another hardware thread among the plurality of hardware threads is specified for execution.
地址 Kawasaki-Shi, Kanagawa JP
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