发明名称 |
MULTIISTEP DIVISION CIRCUIT |
摘要 |
PURPOSE:To realize the low power consumption as well as a higher degree of integration by having the different constitutions between the 1/2-division circuit used to the first step and that used to the subsequent steps in case the multi-step connection is secured for the 1/2-division circuit consisting of the gate using I<2>L. CONSTITUTION:The T-type flip-flop circuit is used for 1st 1/2-division circuit 1 used to the first step, and the circuit comprising four I<2>L gates G11-G14 is used for the 1/2-division circuits used to the subsequent steps respectively. The clock pulse of 2nd 1/2-division circuit 2 is not drawn out of gate G3 and G4 forming the output ratch circuit of circuit 1 but out of gate G1 and G2. As a result, the duty ratio is down to 50% or less (about 25% in this example) for the input part pulse of gate G1 which delivers the clock pulse. |
申请公布号 |
JPS54161872(A) |
申请公布日期 |
1979.12.21 |
申请号 |
JP19780071091 |
申请日期 |
1978.06.13 |
申请人 |
TOKYO SHIBAURA ELECTRIC CO |
发明人 |
AOKI KIYOSHI |
分类号 |
H03K23/52;H03K23/00;H03K23/58;(IPC1-7):03K23/30 |
主分类号 |
H03K23/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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