发明名称 ERROR DETECTION SYSTEM
摘要 PURPOSE:To enhance the error check efficiency by giving the check even to the error occurring within the device which carries out the error check. CONSTITUTION:The reception data given from MODEM7 is sent to CRC check circuit 5 and output register 2 via reception buffer 1, and circuit 5 gives the error check to the reception data. While register 2 produces the prescribed data and transfers it to the processor. In this case, CRC arithmetic circuit 3 performs the operations in sequence based on the data given from register 2. Comparator 4 gives a comparison between the CRC data given from buffer 1 and the operation result of circuit 3. And in case no coincidence is obtained, the occurrence of the error is decided within communication control unit 8 to deliver error signal 6. Thus the error occurred even within the device performing the error check for the supplied data can be detected, accordingly enhancing the error detection efficiency for the data transmission system.
申请公布号 JPS5553940(A) 申请公布日期 1980.04.19
申请号 JP19780126255 申请日期 1978.10.16
申请人 HITACHI LTD 发明人 SAKURAI SHIGERU;SUWA SHIGETOSHI
分类号 H04L1/00;H04L29/02 主分类号 H04L1/00
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