| 摘要 |
PURPOSE:To make it possible to detect securely even an error occurring in a short time by providing a gate circuit which allows the output of a parity checker to pass through for a certain time and circuit which stores temporarily a parity-error occurrence output signal. CONSTITUTION:When the total number of bits of logic ''1'' of data on data bus 1 is odd, partiy checker 2 outputs signal 3 of level ''H'' to NAND gate 14 as a parity error. Gate 14 is applied with strobe signal 13 of level ''H'' as long time as the rightness of data should be secured. Normally, reset signal 17 of level ''H'' is applied to the R terminal of RS-FF16, and no error signal is outputted from checker 2, so that while the output of gate 14 is held at level ''H'', that of FF16 will be at level ''L''. If a short-period error would occur at this time, the output of gate 14 changes into level ''H'' and the output of FF16 increases up to level ''H'', and even after the error disappears afterward, the output of FF16 is held at level ''H'', so that the error occurring when the rightness of data is secured will be latched definitely. |
