| 摘要 |
PURPOSE:To eliminate the detour of a wire in a semiconductor integrated circuit device adapted for an automatic wiring by so arranging a plurality of cells in a checkered pattern as to be displaced with each other on a chip when laying out the cells with a master slice method. CONSTITUTION:When ICs are laid out on a chip with a master slice method, respective cells CEL are so arranged in a checkered pattern as to be displaced with each other. That is, when respective cells CELa and CELb are arranged on a chip having input and output terminals i and o as well as wiring area Ocon, they are aligned in checkered pattern to be displaced with each other. In this manner, the wires for connecting the input and output terminals i and o of these cells may include Y- direction wires y1, y2 of first layer and X-direction wires x1, x2 of second layer to be inclusive only four wires so as to reduce the number of wiring channels and to also eliminate the conflict of these wires each other. |
