发明名称 TWO PHASE LEVEL CODE DEMODULATING CIRCUIT
摘要 PURPOSE:To increase the reliability with a simple circuit, by latching a waveform at leading and trailing of a clock signal reproduced from a two-phase level code with a latch circuit. CONSTITUTION:A two-phase level code signal is inputted to a monostable multivibrator 16 via a waveform shaping circuit 10 and the 1st differentiation circuit 12 and the like. A clock signal C is reproduced with an output pulse of the multivibrator 16 and it is inputted to a clock input terminal CK of the 3rd D latch circuit 20 to latch a waveform-shaped output signal with a waveform shaping circuit 11 and a signal S1 is outputted from an output terminal Q. Similarly, an inverted clock signal C' outputs a signal S2 via a D latch circuit 19. Output signals S1 and S2 of the latch circuits 19 and 20 are inputted to an exclusive logical sum circuit 21, and an output signal S3 is latched at the trailing of the clock signal C of the monostable multivibrator 16 via a latch circuit 17 to obtain a demodulated data. Thus, the reliability can be increased with a simple circuit.
申请公布号 JPS57150118(A) 申请公布日期 1982.09.16
申请号 JP19810033806 申请日期 1981.03.11
申请人 TOKYO SHIBAURA DENKI KK 发明人 YOSHITOME SEIYUKI
分类号 H03M5/04;G11B20/14;H03M5/12;H04L25/49 主分类号 H03M5/04
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